Wildcard TE410P (4th Gen) SS7 got event: HDLC Abort(6) on span 1/0

[amrin]

it gets up but after a few seconds because of so many errors the link goes down

/etc/init.d/system.conf
span=1,1,0,ccs,hdb3,crc4
bchan=2-31
mtp2 = 1
if i change it to hardhdlc i get a lot of hdlc overruns , why ?
/chan_dahdi.conf
/opt/asterisk16_wv_1/etc/asterisk/chan_dahdi.conf
[trunkgroups]

[channels]
echocancel=no
echocancelwhenbridged=no
usecallerid=yes
hidecallerid=no
callwaiting=yes
usecallingpres=no
callwaitingcallerid=yes
threewaycalling=yes
transfer=yes
canpark=yes
cancallforward = yes
callreturn = yes
relaxdtmf = yes
dtmfmode = auto
context = wv_in
signalling = ss7
ss7type = itu
ss7_called_nai = dynamic
ss7_calling_nai = dynamic
ss7_internationalprefix = 00
ss7_nationalprefix = 0
switchtype = national

group = 1
linkset=1
networkindicator = national
pointcode= 2378
adjpointcode = 2781
defaultdpc = 2452

; 1 - 2
cicbeginswith=2
channel=2-31
slc=0
sigchan=1

regarding this topic many says that it is the irq interupts or cable fault
but i checked the irq and i did a loopback cable on ports and they are ok

is there any chance that this have be a software issue in bit error rate because software missdecoding ?
dahdi version
dahdi_cfg -v
DAHDI Tools Version - 2.11.1

DAHDI Version: 2.11.1
Echo Canceller(s):
Configuration

dmesg output :
[13525125.421251] dahdi: Version: 2.11.1
[13525125.421762] dahdi: Telephony Interface Registered on major 196
[13525125.429852] wct4xxp 0000:06:08.0: Firmware Version: c01a016c
[13525125.430758] wct4xxp 0000:06:08.0: FALC Framer Version: 2.1 or earlier
[13525125.430931] wct4xxp 0000:06:08.0: Found a Wildcard: Wildcard TE410P (4th Gen)
[13525125.430975] wct4xxp 0000:06:08.0: VPM450: Not Present
[13525125.705658] dahdi_devices pci:0000:06:08.0: local span 1 is already assigned span 1
[13525125.705661] dahdi_devices pci:0000:06:08.0: local span 2 is already assigned span 2
[13525125.705663] dahdi_devices pci:0000:06:08.0: local span 3 is already assigned span 3
[13525125.705665] dahdi_devices pci:0000:06:08.0: local span 4 is already assigned span 4
[13525125.764050] wct4xxp 0000:06:08.0: TE4XXP: Span 1 configured for CCS/HDB3/CRC4
[13525125.764122] wct4xxp 0000:06:08.0: RCLK source set to span 1
[13525125.764127] wct4xxp 0000:06:08.0: Recovered timing mode, RCLK set to span 1
[13525125.764193] wct4xxp 0000:06:08.0: SPAN 1: Primary Sync Source
[13525125.795880] wct4xxp 0000:06:08.0: TE4XXP: Span 2 configured for CAS/HDB3
[13525125.795949] wct4xxp 0000:06:08.0: RCLK source set to span 1
[13525125.795954] wct4xxp 0000:06:08.0: Recovered timing mode, RCLK set to span 1
[13525125.822989] wct4xxp 0000:06:08.0: TE4XXP: Span 3 configured for CAS/HDB3
[13525125.823043] wct4xxp 0000:06:08.0: RCLK source set to span 1
[13525125.823048] wct4xxp 0000:06:08.0: Recovered timing mode, RCLK set to span 1
[13525125.850783] wct4xxp 0000:06:08.0: TE4XXP: Span 4 configured for CAS/HDB3
[13525125.850832] wct4xxp 0000:06:08.0: RCLK source set to span 1
[13525125.850837] wct4xxp 0000:06:08.0: Recovered timing mode, RCLK set to span 1
[13525128.343183] wct4xxp 0000:06:08.0: Setting yellow alarm span 2
[13525128.343202] wct4xxp 0000:06:08.0: RCLK source set to span 1
[13525128.343206] wct4xxp 0000:06:08.0: Recovered timing mode, RCLK set to span 1
[13525128.371023] wct4xxp 0000:06:08.0: Setting yellow alarm span 3
[13525128.371045] wct4xxp 0000:06:08.0: RCLK source set to span 1
[13525128.371049] wct4xxp 0000:06:08.0: Recovered timing mode, RCLK set to span 1
[13525128.398989] wct4xxp 0000:06:08.0: Setting yellow alarm span 4
[13525128.399003] wct4xxp 0000:06:08.0: RCLK source set to span 1
[13525128.399006] wct4xxp 0000:06:08.0: Recovered timing mode, RCLK set to span 1
[13525635.394351] wct4xxp 0000:06:08.0: TE4XXP: Span 1 configured for CCS/HDB3/CRC4
[13525635.394442] wct4xxp 0000:06:08.0: SPAN 1: Primary Sync Source
[13525635.394644] wct4xxp 0000:06:08.0: RCLK source set to span 1
[13525635.394649] wct4xxp 0000:06:08.0: Recovered timing mode, RCLK set to span 1

this is an old card i gues there should a software issue that some of you guys encountered and can help me with that
is there a need to use chan_ss7.so or chan_dahdi.so cause both provide ss7 functionality

cables i changed they are new
flap ~each 3 minutes

[david551]

Hardware problem, incorrect timing source, etc.

[amrin]

thanks for reply
but you see the timing source is from provider as indicated here span=1,1,0
here i guess i have only 2 choises 1 or 0 for timing , right ?

or beside this string in system.conf , there should be another timing configuration ?
please David help identify the problem as it is hard to identify which is the faulty part here

Hardware problem: if the loopback was green light on all ports does it mean that the card is ok and no further inspects are needed on phisycal part ?

the link wouldnt be UP at all if the card would have been broken
any suggestions on what can i di further to solve this ?

[david551]

I don’t know enough about this sort of configuration on Asterisk to say much more, but HDLC is a physical layer problem. The most common cause is the sequence of signalling states coming off the line is invalid, which is typically for the reasons I gave, but it could also be that the sender chose to abandon sending a frame, which seems unlikely.

HDLC frames are delimited by a signalling state sequence of, if I remember correctly, 01111110. Spoofing of this is avoided by inserting extra 0 states. If the receiver sees 01111111, they will treat this a an abort, and discard the partially received frame. This can happen because the sender deliberately aborted, because a 0 got misread as a 1, or because signalling units are being sampled at the wrong point causing general misreads of the state.

[amrin]

so i guess i have to solve it with telco side but they keep saying that everything is ok on their side and no changes made cause half a year ago everything worked just fine

thats why i think its server/soft related issue after restart
regarding hdlc i appreciate very much the onfo you provided me with , i will keep looking into that but dont know if it is possible to make some changes to modify mtp2 timing or bit stuffing locally
i would like to avoid hdlc but mtp2 works with it and using hardhdlc with ss7 is not an option

so i guess nothing can be done
but i am searching the whole internet and i hope i will find something
i just thought you guys here now better the flow regarding dahdi + ss7 over E1 lines and can give me some hints on how to aproach the issue
maybe disable in code hdlc or try different timers ?
thank you very much anyway
if you have some ideas or suggestion please let me know
any info is appreciated

[amrin]

hey David
i was able to take a ss7 dump from linux with dahdi_pcap on 1st channel which is assigned for signaling
can you please give some explanations regarding this ?